Current Research Project
(Click here for a full list of my past research projects.)
Orthogonal Frequency Division Multiplexing (OFDM) Optical Wireless Communications
This project aims to build a LED-based free-space optical network utilizing the OFDM (Orthogonal Frequency Division Multiplexing) technique. We use cheap visible light LED (light-emitting diode) as transmitters. The wide modulation bandwidth (~10M) of LED along with the high spectral efficiency of OFDM technique makes high speed free-space optical communication possible. As the OFDM modem is computationally intensive, typical implementations are ASIC or FPGA designs. We aim to show that an OFDM modem on a Graphic processor unit (GPU), a massively parallel commodity co-processor, can serve as an alternative to ASIC or FPGA designs and deliver impressive throughput.
This project is an extension of my “Optoelectronics Information Comprehensive Experiment” coursework project. In the coursework project, our group presented a prototype of LED visible light communication system using OFDM technique, and established a set of protocol and an encoding/decoding scheme specially designed for LED OFMD application. We combined OFDM with the QAM modulation and convolution code for high bandwidth efficiency and low bit error rate. A data transfer rate of up to 56 kbps over a 20 kHz channel was achieved. The result is limited by the narrow bandwidth of our AD/DA convertors; however, it predicts a promising result of more than 10Mbps if we generalize our result to the full bandwidth of LED.
ARM System-on-Chip on Xilinx FPGA
2011.10 - Present
This is not a very big project. I helped Prof. Xiaohong Jiang build a tiny ARM system based on the open-source Amber Core for her Computer Architecture class. The Amber Core was originally targeted to Spartan-6 FPGA, but as we didn't have adequate Spartan-6 boards for teaching, I ported Amber to our Spartan-3E Starter Kit. Because there were many differences between these two FPGA generations and our FPGA had much less logic gates, some modification and simplification were necessary. I also rewrote and optimized some part of the code, such as an improved barrel shifter utilizing embedded multipliers to reduce resource usage. Eventually the 3-stage pipelined Amber processor was able to run on a resource-limited Sptartan-3E500 FPGA. I understood how to utilize the FPGA's special resources (such as BlockRAM, embedded multipliers) to implement processors efficiently. Currently I am writing an educational document for this system and hopefully it can be used in Prof. Xiaohong Jiang's class next year.
Past Research Project
You can find detailed descriptions of my past research projects here.